1. Field of the Invention
This invention relates to a read-write semiconductor memory such as a DRAM, and more particularly to a semiconductor memory with an external input data taking-in circuit for taking in external data for testing.
2. Description of the Related Art
In the field of semiconductor memories, particularly DRAMs (dynamic random access memories), as their memory capacity has increased and more and more circuits have been squeezed into smaller spaces, a wide variety of DRAMs have been put on the market. Most of conventional general-purpose DRAMs are written into and read from bit by bit or in units of 4 bits. However, now that their access time (or cycle type) has reached the limit, various multi-bit products are being required for processing a large volume of data. In this situation, it is necessary to shorten the testing time and simplify the testing of the product.
As an example of a multi-bit product, a semiconductor memory capable of being written into and read from in units of 4 bit is shown in FIG. 1. The semiconductor memory contains four external input data taking-in circuits (DIB1 to DIB4) (hereinafter, referred to as data input buffers) 10. These four data input buffers 10 have the same internal construction. In the test mode, each of them takes in external data and supplies the data to a memory cell array 11. In the normal operation mode, the data input buffers exchange read and write data with the memory cell array 11.
The memory cell array 11 is composed of DRAM memory cells and a peripheral circuit for controlling the writing and reading of data into and from these memory cells. In the test mode, the data loaded into the individual data input buffers 10 and then written into the memory cell array 11 is read from the memory cell array 11. This read-out data is compared with the original data before writing by a comparison circuit (not shown) to test the memory cells for defects.
Like the case where data is written or read in units of 4 bits, when in a multi-bit product with a small number of parallel bits, data is written in the test mode as in the normal operation mode, no problem is encountered in providing as many data input buffers of the same circuit arrangement as the number of bits and writing data bit by bit independently. Even when the data supplied to an external data input pad is written equally into all the data input buffers to simplify the test, no problem occurs with a multi-bit product with a small number of bits as when data is written or read in units of 4 bits.
However, in the case of multi-bit products with a larger number of bits, an increase in the input capacity becomes a problem. Specifically, because many data input buffers are connected to a single external input pad, the input capacity for the pad increases. The increase in the input capacity elongates the time required to set write data, resulting in an increase in the testing time.
More and more semiconductor memories operating on low voltages, e.g., semiconductor memories operating from a power supply voltage of 3.3 V, will possibly be used in the future with conventional semiconductor memories, however, the data is transferred through the series source-to-drain passes of two n-channel MOS transistors in a data input buffer during the test mode. As a result, also in a normal data write operation, the data is transferred through the source-to-drain passes of two n-channel MOS transistors in the data input buffer. However, in the case of low-voltage products such as semiconductor memories operating from a power supply voltage of 3.3 V, it is difficult to apply a gate voltage high enough to turn on the two MOS transistors properly. This leads to a possibility that the potential of write data will drop by the threshold voltages of the two n-channel MOS transistors. In the data input buffer, however, a reference potential compared with the potential of external data is transferred through the source-to-drain pass of a single n-channel MOS transistor. This permits the reference potential to drop only as much as the threshold voltage of the single n-channel MOS transistor. As a result, depending on conditions, there is a possibility that the opposite of the proper data will be transferred to the memory cell array.